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1 GHz Reference clock

DOUBLE DDS

Giuliano, I0CG has developed 1 GHz reference clock circuit which I used in a similar design during DDS testing. As a 100MHz source ABRACON Ultra Low Phase Noise VCXO was choosed. It was a compromise between quality parameters and the price (-118 dBc/Hz @ 100Hz offset). In XO configuration, the Phase Noise will be slightly better at each offset between 10Hz and 10 kHz, by approximately -3dB to -5dB.

Inspired by Martein, PA3AKE, I decided for advanced solution and I suggested PCB with 100MHz Abracon ABLNO VCXO, LTC6752, MCL SYK-2R doubler, double and tripple helical selectivity filters ordered from RF Microwave, two-stage amplification with SGA4586Z,  MCL  HPF HFCN-880+, LPF LFCN-1000+ and output divider. The output level of the 1 GHz reference clock is abt. +5 dBm at every output. Second version of 1 GHz reference clock was assembled to a special home made screening box.


First version of 1 GHz Reference clock, used during DDS testing.


Second version of 1 GHz reference clock.  At the bottom side of the board, next to the MCL doubler,  MCL HPF and LPF are visible (size 1206).


On the following pictures Reference clock level and subharmonics are shown. 100MHz and 500 MHz subharminics are 135 dB or more below the carrier, 1500 MHz harmonic is more than 120 dB below the carrier. Second harmonic is suppressed against the carrier 43.7+ 4.7 = 48.4 dB. Third harmonic is suppressed 52.4 + 4.7 = 57.1 dB against the carrier.  Although it was LPF used behind the second amplifier, the level of the 2nd and 3rd harmonics seem to be still high.  Therefore one more LPF  (F8) will be used in the final board, as indicated  in the final version of the schematic.                   


For comparison I measured levels of the 2nd and 3rd harminics (second version of the reference board)  with Rohde&Schwarz Spectrum Analyzer FSH6, too. Attenuator 20 dB was used at the SA input to eliminate eventual parasitic products.  Second harmonic was suppressed  48.1 dB and third harmonic 55.3 dB below the carrier (level +5.6 dBm). The results are in good agreement with previous measurements.

The measurement results on the final sample.


Final sample was made with two LPFs (F4, F8) and one HPF (F7) in the chain. Rohde&Schwarz Spectrum Analyzer FSH6 with Attenuator 20 dB  at the SA input (to eliminate eventual parasitic products)  was used for measurements.


Carier level is +5.4 dBm. Subharmonic and harmonic suppresion is min. 70 dB on 100 MHz, 500Mhz, 1500MHz and 3000 MHz. Second harmonic level reached -60 dBc. Level of harmonics are significantly better than in the second sample.

Conclusion. Final version of the 1GHz Reference clock reached very good parameters compare to all of previous tested samples. I will use just one output. In the case if another output must be used, PCB is prepared for divider parts adding.

 
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